This application claims the priority benefit of Taiwan application serial no. 91208321, filed on Jun. 5, 2002.
1. Field of Invention
The present invention relates to a flip-chip package substrate and a flip chip die.
More particularly, the present invention relates to a flip-chip package substrate capable of boosting electrical performance and reducing packaging area and a flip chip die for joining with the flip-chip package substrate.
2. Description of Related Art
Flip chip interconnect technology is a method of joining a chip and a carrier together to form a package. The chip has an array of die pads each having a bump thereon. After the chip is flipped over, the bumps on the die pads are made to bond with contacts on the carrier so that the chip is electrically connected to the carrier via the bumps. The carrier also has internal circuits leading to external electronic devices. Since flip chip packaging technique is suitable for packaging high pin count chips and capable of reducing packaging area and shortening signal transmission paths, flip-chip technology has been applied quite widely to the manufacturing of chip packages. At present, chip packages that utilize flip-chip technique include flip-chip ball grid array (FCBGA), flip-chip pin grid array (FCPGA), chip-on-board (COB) and so on.
FIG. 1 is a schematic cross-sectional view of a conventional flip-chip ball grid array package. As shown in FIG. 1, a plurality of die pads 14 for transmitting signals to or from the chip is formed on the active surface 12 of a chip 10. A bump 30 for connecting with the bump pad 24 on the upper surface 21 of a flip-chip package substrate 20 is also formed on top of each die pad 14. In addition, the flip-chip package substrate 20 comprises a plurality of patterned conductive layers 23 and a plurality of insulating layers 26 alternately stacked over each other. The insulation layers 26 also have a number of conductive plugs 28 that pass through the insulation layers 26 for electrically connecting two or more conductive layers 23. The conductive plugs 28 are, for example, plating through holes (PTH) 28a and conductive vias 28b. Furthermore, the bump pads 24 on the upper surface 21 of the flip-chip package substrate 20 are actually the uppermost layer (the conductive layer 23a) of the conductive layers 23. A solder mask 27a covers and protects the conductive layer 23abut exposes the bumps 24.
The bottom surface 22 of the package substrate 20 has a plurality of ball pads 25 thereon. The ball pads 25 are actually the exposed portion of the bottom most (the conductive layer 23b) of the conductive layers 23. A patterned solder mask layer 27b covers and protects the conductive layer 23b but exposes the ball pads 25. Solder balls 40 or other conductive structures may be attached to the ball pads 25 for electrically connecting to the external devices. In brief, the die pads 14 on the chip 10 are electrically connected to a next-level electronic devices such as a printed circuit board (PCB) through the bumps 30, the bump pads 24, various conductive layers 23 and various conductive plugs 28, ball pads 25 on the bottom surface 22 of the flip-chip package substrate 20 and the solder balls 40.
FIG. 2 is a top view of the chip in FIG. 1 and FIG. 3 is a partial top view of the flip-chip package substrate in FIG. 1. As shown in FIG. 2, the die pads 14 are organized into an area array on the active surface 12 of the chip 10. According to functions, the die pads 14 can be divided into signal pads 14a, power pads 14b, ground pads 14c, and core power/ground pads 14d. The signal pads 14a, the power pads 14b, and the ground pads 14c are distributed non-specifically around the core power/ground pads 14d. 
As shown in FIG. 3, the bump pads 24 are similarly organized into an area array format on the upper surface 21 of the flip-chip package substrate 20 so that they correspond with various die pads 14 on the chip 10. Note that the bump pads 24 can be similarly divided according to their respective functions into signal bump pads 24a, power bump pads 24b, ground bump pads 24c and core power/ground bump pads 24d. The signal bump pads 24a, the power bump pads 24b and the ground bump pads 24c are distributed non-specifically around the core power/ground bump pads 24d. 
As shown in FIGS. 2 and 3, the die pads 14 are organized regularly into an area array on the active surface 12 of the chip 10 with the bump pads 24 on the flip-chip substrate 20 arranged similarly to correspond to such an array arrangement. Note that neighboring bump pads 24 must have a pitch greater than the permitted processing limit and/or the minimum width for passing a conductive line between these two bump pads 24. Furthermore, the die pads 14 on the chip 10 must correspond to the positions of the bump pads 24 on the flip-chip substrate 20. Hence, the chip 10 must provide a sufficiently large area to accommodate all the die pads 14 rendering any further reduction of chip area difficult. Furthermore, because various die pads 14 having a specific function (such as the signal pads 14a, the power pads 14b and the ground pads 14c) are non-specifically positioned on the active surface 12 of the chip 10, redistribution wiring for the chip 10 is increased. Correspondingly, overall wiring length inside the flip-chip substrate 20 is also increased. Ultimately, electrical performance after joining the chip 10 and the flip-chip package substrate 20 together is severely compromised.
Accordingly, one object of the present invention is to provide a flip-chip package substrate and a flip chip die. Through a rearrangement of the bump pads on the flip-chip package substrate, electrical performance of the chip inside the package is improved and area required to form the chip is reduced so that the cost of producing each monolithic chip is lowered.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a flip-chip package substrate. In the flip-chip package substrate, signal bump pads, power bump pads and ground bump pads are grouped together into rows of inner layer bump pads and sequentially laid on the same side just outside the gathering of core bump pads so that the row of power bump pads and the row of ground bump pads are alternately positioned between the row of signal bump pads. Hence, electrical performance after joining the chip and the flip-chip package substrate is improved. In addition, positions of the outer layer of the bump pads are designed using the shortest distance that corresponds to the flip-chip package substrate so that the flip chip die connecting area within the flip-chip package substrate is reduced.
This invention also provides a flip chip die. The flip chip die has a plurality of die pads on the active surface of the chip. The die pads are positioned on the chip according to the distribution of the bump pads on the aforesaid flip-chip package substrate. Hence, electrical performance of the chip is improved and size of the chip is reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.